Open Innovation Platform® |
TSMC Open Innovation Platform® Accelerates Your Innovation
With Comprehensive IP Portfolio, Design Tool Readiness, Technology and Service Maturity
TSMC is holding its 2019 Open Innovation Platform® (OIP) Ecosystem Forum in September, the largest annual event of its kind bringing together the semiconductor design chain community and TSMC customers, and demonstrating how TSMC and its ecosystem partners jointly develop design solutions on top of TSMC’s advanced technologies through OIP collaboration. The OIP Ecosystem Forum provides an interactive platform for OIP Alliance partners and customers to highlight their progress and their collaboration with TSMC in addressing advanced process node requirements and challenges for silicon innovations, focusing on Mobile & Automotive, High-Performance Computing & 3DIC, and IoT & RF.
TSMC’s OIP ecosystem is an important factor in empowering customers to unleash their innovations with fast time-to-market. TSMC’s Open Innovation model brings together the creative thinking of customers and partners under the common goal of shortening design time, time-to-volume, time-to-market and ultimately, time-to-revenue. In October 2018, TSMC launched its OIP Virtual Design Environment (OIP VDE) that allows customers to design in a secure and safe cloud environment that significantly increases their design productivity. In addition, the OIP VDE greatly lowers entry barriers for customers of all sizes to enable their “Design-in-the-Cloud” through TSMC’s close collaboration with its OIP Cloud Alliance partners - Amazon Web Services (AWS), Cadence, Google Cloud Platform (GCP), Mentor, Microsoft Azure and Synopsys. The Company continued to work with its ecosystem partners to expand its libraries and silicon IP portfolio to more than 21,000 items.
Size Enables Customer Choice
TSMC’s OIP is the foundry segment’s largest design support ecosystem with 42 IP Alliance partners, 22 EDA Alliance partners, 19 Design Center Alliance Partners, 7 Value Chain Aggregators Alliance partners, and 6 Cloud Alliance Partners. The Company also has foundry’s earliest and most comprehensive electronic design automation (EDA) certification program, delivering timely design tool enhancement required by new process technologies. The size of our OIP ecosystem provides customers with the broadest range of choice and flexibility, making it possible to satisfy customer’s requirement on any design tools or partner to be actively supported and monitored.
Capability for Joint Development
TSMC and its partners work together proactively and engage much earlier and deeper than ever before in order to address mounting design challenges at advanced technology nodes. Through this early and intensive collaboration effort, TSMC’s OIP is able to deliver the needed design infrastructure with timely enhancement of EDA tools, early availability of critical IPs and quality design services when customers need them. Taking full advantage of the process technologies once they reach production-ready maturity is critical to customers’ success. Joint methodology development starts well in advance of process development, resulting in many features specific to TSMC technology – and available first in TSMC processes.
Industry’s Most Comprehensive IP Portfolio
As the world’s largest semiconductor foundry, TSMC has the most comprehensive process technology roadmap supported by the foundry segment’s largest, most comprehensive and most robust silicon-proven IP and library portfolio, which currently consists of over 21,000 IP “titles.” Each of these IP titles could be a large complex IP like an ARM A72 core, or a collection of standard cells in a library -- a library with thousands of standard cells would be one IP “title.” Virtually whatever IP customer’s needs are supported, or can be quickly developed in partnership with IP Alliance members. And that IP portfolio is still growing.
Assurance of Design Tool
Design tool assurance is one of the most important features of OIP, which is implemented through Individual Tool Certification (ITC), Integrated Tool Flow (ITF), and Reference Flow (RF) certification. TSMC ensures that each individual EDA tool in the OIP offers results correlated to TSMC silicon, and also validates the integration of these tools across the full design flow with real-world design examples fabricated in TSMC silicon. Since 2012, Reference Flow has become node-specific to increase EDA tool integration and synchronization with TSMC process development. Moreover, the Company’s deep and close collaboration with ecosystem partners in the past 18 years is a great example of how to ensure the readiness of design tools and IP for each major node, and the maturity of technologies for customer’s silicon innovation. The readiness of design ecosystem solutions helps customers design applications to capture market opportunities in high-growth markets such as mobile, high-performance computing, the Internet of Things and automotive.
With over 20 years’ experience in reference flow development, TSMC has a long history of working with ecosystem partners, and those partners know how to work effectively with TSMC to unleash our customers’ silicon innovation in a cost-effective way and realize faster time-to-market. Innovation has always been an exciting and challenging proposition. Competition among semiconductor companies continues to grow more intense in the face of increasing industry consolidation and the commoditization of more mature and conventional technologies. Companies must find ways to keep innovating in order to survive and prosper. One way to accelerate innovation is through active collaboration with external partners, and OIP is TSMC’s answer.
For more information about TSMC Open Innovation Platform® , please visit our website at: https://www.tsmc.com/english/dedicatedFoundry/oip/index.htm
TSMC OIP VDE: Comprehensive, Cost Effective, Secured
Most Comprehensive Design Enablement Platform Benefits Customers of all sizes
TSMC has announced its OIP Virtual Design Enablement (OIP VDE) for almost a year, receiving overwhelmingly positive feedback from customers of all sizes for helping them realize their silicon designs and creations in TSMC’s leading-edge technologies in an efficient, cost-effective and secure fashion. Customers have taped out their 7nm products using solutions from TSMC’s Cloud Alliance, and TSMC even used it for its own 5nm development to speed up memory, standard cell, and EDA design infrastructure deliveries to customers. This innovative collaboration with TSMC OIP ecosystem partners further enhances customer productivity by leveraging the flexibility and power of the cloud, and lowers the barriers for customers of all sizes to enable their “Design-in-the-Cloud” through TSMC’s close collaboration with its OIP Cloud Alliance Partners - Amazon Web Services (AWS), Cadence, Google Cloud Platform (GCP), Mentor, Microsoft Azure and Synopsys.
In TSMC’s enablement of OIP VDE, both digital RTL-to-GDSII and custom schematic-capture-to-GDSII design flows have been validated along with OIP design collateral, including process technology files, PDKs, foundation IP and reference flows. To ensure low barriers for customer “Design-in-the-Cloud” adoption with entry level to high level technical support, OIP Cloud Alliance partners like Cadence, Mentor and Synopsys act as focal points to help customers set up VDE and provide first-line support.
Q: What is TSMC OIP VDE and how does it help customers of all sizes?
TSMC OIP VDE is a TSMC certified design environment on cloud, helping customers fully utilize the performance, capacity, and availability of cloud computing power, memory and storage to best match customers’ project resource requirements, whether they are startups or major global enterprises, and securely conduct IC design in TSMC technologies with OIP design collaterals.
As a proven design environment in the cloud, OIP VDE has been certified by TSMC with its OIP ecosystem partners to lower adoption barriers for designers new to the cloud usage in the following ways: (1) EDA software, IT infrastructure and technical support are included and ready for use (2) customized to satisfy each individual design project’s actual demands (3) one-stop shop through VDE storefronts operated by EDA partners.
Q: Security is one of the most critical considerations in moving IC design to the cloud. Who are TSMC’s certified cloud service providers for OIP VDE that customers can choose from?
TSMC has gone through rigorous cloud security exercises with Amazon Web Services as well as Microsoft Azure, and both became TSMC certified cloud service providers for OIP VDE when the program was announced last October. In May 2019, TSMC OIP VDE with EDA tools was certified and available on Google Cloud Platform (GCP), a new member of TSMC’s Cloud Alliance. The combination of these cloud technologies gives customers’ System-on-Chip (SoC) teams access to EDA tools, IP, and TSMC design collateral -- including process technology files, process design kits (PDKs) and foundation IPs, to be used on all three cloud platforms.
Q: How does customer work with OIP VDE and achieve its benefits?
TSMC’s certified EDA partners will work with cloud service providers of our customers’ choice to architect the design environment in the cloud based on their design project requirements. With all the design data, TSMC design collaterals, EDA tools, computing power and storage ready in the VDE, the customers are now ready to carry out their design through remote access.
Through a recent joint project with Mentor, Microsoft Azure and TSMC, a 5nm test chip from TSMC took less than four hours to complete its verification thanks to the productivity boost enabled by Mentor’s Calibre in the cloud. This performance demonstrates how the power of cloud computing, combined with TSMC know-how and our partners’ innovation, can provide mutual customers with additional options for optimizing tape-out schedules.
Q: What is the EDA coverage of OIP VDE?
TSMC started with two full-flow EDA partners, Cadence and Synopsys, and Mentor joined the Cloud Alliance this April with its new cloud-ready design solutions, broadening TSMC’s OIP ecosystem and helping customers unleash innovations with TSMC process technologies. All three announced their design tool certification on TSMC’s advanced processes up to 5nm in April 2019, providing the most comprehensive readiness for customers’ silicon innovation.
Q: What kind of design implementations and which EDA tools have been tested on TSMC’s
OIP VDE?
Both Digital and Custom design flows have been validated with TSMC reference flows in conjunction with TSMC process technology files, PDKs and foundation IPs. In VDE technical validation, TSMC goes end-to-end covering cloud chamber setup, network connection, data transfer, remote access, all the way to the EDA tool performance and accuracy on cloud.
TSMC OIP Innovation Partners
