TSMC Says Immersion Lithography Nearly Production Ready
Proprietary Techniques Produce Near-Zero Defect Rates
Hsinchu, Taiwan, R.O.C. – February 22, 2006 -- TSMC (TAIEX: 2330, NYSE: TSM) today revealed that its immersion lithography program has produced test wafers well within acceptable parameters for volume manufacturing. The findings, to be revealed tomorrow by TSMC researchers at the SPIE Microlithography Conference in San Jose, prove the value of TSMC’s proprietary techniques for nearly defect-free immersion lithography.
“Our goal is always zero defects,” said Burn Lin, senior director of TSMC’s micropatterning division and a recognized immersion lithography expert. “Recently, TSMC produced multiple test wafers with defects rates as low as three per wafer – better than any other immersion results to date, and comparable to the very best dry lithography results. With defect root causes understood, TSMC can now focus on throughput improvement for high-volume manufacturing.”
Immersion techniques extend the useful life of current-generation lithography systems, the large, multimillion-dollar, camera-like machines that are the heart of semiconductor manufacturing. The ability to extend the usefulness of these machines is considered crucial to enabling future generations of semiconductor manufacturing, as alternative lithography systems are much further from production-worthiness.
Immersion lithography systems use water, or a similar clear liquid, as an image-coupling medium. By placing water between the lithographic lens and the semiconductor, engineers can preserve higher-resolution light from the lens, enabling smaller, more densely-packed devices.
But liquid mediums present their own challenges, including defects such as bubbles, watermarks, particles, particle-induced printing defects, and resist residue. TSMC’s R&D researchers resolved these issues by developing a proprietary defect-reduction technique that, on initial tests, produced less than seven immersion-induced defects on many 12-inch wafers, a defect density of 0.014/cm2. Some wafers have yielded defects as low as three per wafer, or 0.006/cm2. This compares to several hundred thousand defects produced by a prototype immersion scanner without these proprietary techniques and significantly better than published champion data in double digits.
TSMC’s immersion lithography technology is targeted at TSMC’s 45nm manufacturing process.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to run 65nm customer design prototype wafers. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.